New standards of high speed input/output (I/O) are the results of the development of dynamic termination transistor logic (DTL). FIG. 1A shows a schematic of single ended DTL data receiver 10 used in a DTL I/O interface. The receiver 10 is used as a single ended input buffer. The signal input DATA is connected with a pull-up termination impedance 14 and power supply voltage VDDO. These components are connected to one of the signal input pins of the comparator 12. The other signal input pin of the comparator 12 is connected to an external voltage reference VREF through a voltage divider. The voltage divider circuit includes a resistor 16 tied to VREF and another resistor 18 tied to ground. The input for the pin of the comparator 12 is taken for a point between the two resistors 16, 18. The comparator 12 generates the signal OUTPUT to be used by the system.
Other configurations of DTL receivers may also be used. FIG. 1B shows a differential DTL clock receiver 20 which is used with DTL synchronous I/O signaling. A differential DTL clock receiver includes a comparator 22 similar to the one used with the receiver shown in FIG. 1A. However, this receiver 20 ties the true clock signal (CLK+) and the complementary clock signal (CLKxe2x88x92) to the input pins of the comparator 22. Each of these clock signals are connected with a pull-up termination impedance 24 and power supply voltage VDDO prior to the respective input pins of the comparator 22. The comparator 22 generates a clock signal (CLK) to be used by the system.
FIG. 2 is a graph showing a synchronous I/O signal 30 as it is output from a driver to a receiver input (DATA) as shown FIGS. 1A or 1B. The signal 30 is represented by the output voltage (VO) 32 verses time. VREF is shown as the center point of the voltage swing. The high voltage output level (VO-H) 34 and the low voltage output level (VO-L) 36 are shown as dotted lines. The difference between the ideal output voltage 32 and VO-H 34 and VO-L 36 is indicative of the effects of the pull-down impedance of the circuit. Additionally, the difference in VO and these high and low output limits determine the noise margin of the signal. Specifically, the difference between VO-H and VREF defines the xe2x80x9chigh noise marginxe2x80x9d and the difference between VREF and VO-L defines the xe2x80x9clow noise marginxe2x80x9d.
FIG. 3 shows a schematic of a prior art conventional I/O DTL system. The system includes a receiver module 42 and a transmitter module 44. These modules are attached to each other by a receiver connector 43 and a transmitter connector 45. The transmitter module 44 shows two separate drivers: a first driver 46 with a pull-down impedance 47; and a second driver 48 with a pull-up impedance 49. The pull-up impedance is attached to the local power source for the transmitter module (VDDO2). While only two drivers 46, 48 are shown, multiple drivers 50 are present on the transmitter module. These multiple drivers 50 will connect will a like number of complementary receivers, not shown, in the receiver module 42.
The receiver module 42 shows two receivers 52, 54 similar to the example shown in FIG. 1A. Each receiver 52, 54 receives input into one of its pins from a corresponding driver 46, 48 in the transmitter module 44. Each of these inputs from the drivers 46, 48 are connected to a respective pull-up impedance 53, 55 which is connected to the local power supply (VDDO1) for the receiver module 42. The other input pin of each receiver 52, 54 is tied to VDDO1 which is connected to the receivers 52, 54 through a pair of voltage divider impedances 55, 56, and 57. These impedances 55, 56, and 57 have a ratio of impedance values of 1:3, respectively. While not shown, the system of FIG. 3 would also include a differential DTL clock receiver as shown in FIG. 1B.
Some problems encountered in signal processing of the I/O DTL system, as shown in FIG. 3, include: noise margin balance; power down awareness; and I/O link floating. Referring back to FIG. 2, the VO-H should ideally be equal to the power supply voltage (VDDO) within xc2x11.5% while the VO-L is determined by the ratio of the pull-up impedance located in a receiver chip and a pull-down impedance in a transmitter chip. If these impedance values are accurately controlled (less than xc2x15% variation), then a conventional local VREF that is generated from a resistor divided network (shown in FIGS. 1A and 3) may be sufficient to provide a somewhat balanced noise margin of the DTL signal. However, if these impedances are loosely controlled (more than xc2x115% variation), then VOL will usually vary from chip to chip according to process variation. As a result, the noise margin (as shown in FIG. 2) will significantly increase and affect the signal quality. In this case a VREF voltage tracking to the changes in VOL will provide a scheme to balance the noise margin.
FIG. 4A shows the effects of power failure in the DTL I/O system 60. As shown previously in FIG. 3, VDDO1 represents the power supply of the receiver module 42 and VDDO2 (not shown) represents the power supply of the transmitter module 44. When VDDO2 fails, the differential input to both receivers 52, 54 will be pulled up to VDDO1 which leads to reliability concerns.
When VDDO1 fails there are two possible states of the receiver: the receivers 52, 54 pull-up impedance 53, 55 is high; or the pull-up impedance 53, 55 is low (normal operation). If the impedance is high, the drivers 46, 48 only see an unterminated interconnect. The excess overshoot and undershoot voltage due to reflection could cause over-voltage stress reliability problems. If the impedance is low, the transient current will flow from the drivers 46, 48 into VDDO1 through parasitic paths which leads to reliability problems such as latch-up and electromigration.
FIG. 4B shows the effects of a power failure within the DTL I/O system 60 on a differential DTL clock receiver 64 as shown in FIG. 1B. When VDDO2 fails, both differential inputs pins will be pulled up to VDDO1. This will result in an undefined differential input. Consequently, any random differential mode noise will result in the clock output oscillating at unknown, including higher than normal, frequencies. This would lead to higher power consumption as well as electro-migration reliability concerns.
The problem of I/O xe2x80x9clink floatingxe2x80x9d occurs when one of the modules 42, 44 is unplugged unintentionally while the other module 42, 44 is still in operation. This condition leads to similar effects as with the power failure conditions as described previously with respect to FIGS. 4A and 4B.
In some aspects the invention relates to an apparatus for generating a reference voltage for an input/output system with a transmitter module and a receiver module, wherein a data transfer occurs between the transmitter module and the receiver module, comprising: a driver component that transmits an output signal; and a receiver component that receives the output signal, wherein the receiver component generates a reference voltage in relation to the output signal.
In an alternative embodiment, the invention relates to an apparatus for generating a reference voltage for an input/output system comprising: a driver module comprising, a driver component that transmits an output signal, a clock driver circuit that transmits a clock signal, and a plurality of data driver circuits that transmit a data transfer; and a receiver module comprising, a receiver component that receives the output signal, wherein the receiver component generates a reference voltage in relation to the output signal, a clock receiver circuit that receives the clock signal, and a plurality of data receiver circuits that receive the data transfer.
In an alternative embodiment, the invention relates to An apparatus for generating a reference voltage for an input/output system with a transmitter module and a receiver module, wherein a data transfer occurs between the transmitter module and the receiver module, comprising: means for transmitting an output signal; and means for generating a reference voltage in relation to the output signal.
In an alternative embodiment, the invention relates to a method for generating a reference voltage for an input/output system comprising: generating an output signal with a driver component; transmitting the output signal from the driver component to a receiver component; and generating a reference voltage with the receiver component, wherein the reference voltage is generated in relation to the output signal.
In an alternative embodiment, the invention relates to a method for disabling a data transfer for an input/output system with a transmitter module and a receiver module, wherein a data transfer occurs between the transmitter module and the receiver module, comprising: generating a driver enable signal with a driver component; and disabling the data transfer with the driver enable signal.
In an alternative embodiment, the invention relates to a method for disabling a data transfer for an input/output system with a transmitter module and a receiver module, wherein a data transfer occurs between the transmitter module and the receiver module, comprising: generating a receiver enable signal with a receiver component; and disabling the data transfer with the receiver enable signal.
The advantages of the invention include, at least: generating a reference voltage for a DTL I/O system that operates over varying system conditions; detecting a power loss for an DTL I/O system and disabling the affected circuits to ensure signal reliability; detecting a unplugged chip for an DTL I/O system and disabling the affected circuits to ensure signal reliability; and activating an alarm when a condition potentially affecting signal reliability occurs.